Conventional stacked capacitor DRAM memory arrays utilize either a buried bit line or a non-buried bit line construction. With buried bit line constructions, bit lines are provided in close proximity to the bit line contacts of the memory cell FETs, with the cell capacitors being formed horizontally over the top of the word lines and bit lines. With non-buried bit line constructions, deep vertical contacts are made through a thick insulating layer to the cell FETs, with the capacitor constructions being provided over the word lines and beneath the bit lines. This disclosure concerns fabrication of memory arrays having buried bit lines.
There is a continuing goal in semiconductor wafer processing to shrink the memory cell size thereby maximizing density. At this writing, the industry is striving to develop a generation of 64 megabyte DRAMs of a conventional chip size. One concern in DRAM processing is the pitch or separation distance between adjacent bit lines and adjacent word lines. For example with respect to bit lines, the bit lines at various points must contact one of the active areas of each cell FET. Such are commonly referred to as bit line contacts. An insulating layer is provided atop the wafer for isolation of the various active regions. Thereafter, bit line contacts are opened to the desired active areas using photolithography techniques. At some point thereafter, bit line material is deposited atop the wafer and patterned to define a desired array of bit lines.
However, a safety factor must be provided for mask misalignment to assure that the bit lines completely overlap the bit contact. This is typically accomplished by enlarging the bit line areas around where the contact etch has occurred to allow for mask misalignment in ensuring adequate contact of the bit lines relative to the bit line contacts.
Such is illustrated in FIG. 1, where a bit line 12 and a bit line contact 14 are illustrated. Where bit line 12 overlies contact 14, an enlarged bit line area 16 referred to as "surround" is provided. This ensures adequate engagement of contact 14 with bit line 12 due to inadvertent mask misalignment of the patterning of bit lines 12 relative to contacts 14. This technique does however have the drawback of an overall widening of the bit lines requiring that bit lines be spaced farther apart from one another than were such surround not present.
With respect to word lines, a problem which works against cell density maximization for buried bit line DRAMs is illustrated in FIG. 2. There illustrated is a wafer fragment 18 having a series of word lines 20, 22 and 24. Also illustrated is a bit line 26. The illustrated cross section has been taken on a diagonal cut through the array, whereby the bit line 26 in FIG. 2 does not appear to run perpendicularly relative to the word lines. In typical prior art fabrication, the word lines are formed first with their associated spacers, such as the illustrated spacers 28. Sometime thereafter, bit line material is applied atop the wafer and etched to define the respective bit lines 26. Insulating spacers must also be provided about the bit lines 26 for electrical isolation purposes. The bit line spacers are designated with numeral 32. During formation of spacers 32, unfortunately additional spacers 34 are added about the already insulated and spaced word lines. Thus, double spacers are formed about the word lines. This requires that the word lines be spaced farther apart than is otherwise desired to provide ample room between word lines for making desired contacts to active areas for the future storage capacitor. Such increase in word line pitch works against density maximization.
Another problem associated with buried bit line formation is the etch which produces the bit line pattern. The bit lines to be formed serpentine up and down perpendicularly over the word lines, thereby having a widely varying topography across the wafer. Etching of layers having widely varying topography requires a significant amount of over etch and is vulnerable to leaving resistive shorts between the bit lines.
It would be desired to overcome these and other aspects of the prior art in forming buried bit line arrays of memory cells.